Nonvolatile semiconductor memory device and method of fabricating the same

ABSTRACT

According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Division of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. Ser. No. 13/227,882, filed Sep. 8, 2011,and is based upon and claims the benefit of priority from prior JapanesePatent Application No. 2011-065282, filed on Mar. 24, 2011, the entirecontents of which are incorporated herein by reference.

FIELD

Embodiments relate to a nonvolatile semiconductor memory device and amethod of fabricating the nonvolatile semiconductor memory device.

BACKGROUND

Developments have been carried out on various types of nonvolatilesemiconductor memory devices having a bit cost scalable (BiCS) structurein recent years. A three-dimensional Bi CS structure achieves anincrease in a memory capacity with lower costs.

A nonvolatile semiconductor memory device having the BiCS structure isproduced by processing a stacked layer body at one operation. The numberof bits can be increased as the layered number is increased. For thisreason, the BiCS structure can decrease costs per bit.

On the other hand, a poly-crystalline semiconductor is used for achannel region in the nonvolatile semiconductor memory device using theBiCS structure. The structure mentioned above entails a problem thatelectron mobility is low in the channel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a nonvolatile semiconductormemory device according to an embodiment;

FIG. 2 is a diagram showing a resistivity of poly-crystalline siliconagainst a concentration of fluorine atoms;

FIG. 3 is a cross-sectional view showing a nonvolatile semiconductormemory device according to the embodiment;

FIGS. 4A to 4F are cross-sectional views showing a method of fabricatinga nonvolatile semiconductor memory device according to the embodiment;

FIGS. 5A to 5D are cross-sectional views showing a method of fabricatinga nonvolatile semiconductor memory device according to the embodiment;

FIGS. 6A to 6D are cross-sectional views showing a method of fabricatinga nonvolatile semiconductor memory device according to the embodiment;

FIG. 7 is a cross-sectional view showing a nonvolatile semiconductormemory device according to the embodiment.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device, including asubstrate, a stacked layer body provided above the substrate, thestacked layer body alternately stacking an insulator and an electrodefilm one on another, silicon pillars containing fluorine, the siliconpillar penetrating through and provided in the stacked layer body, atunnel insulator provided on a surface of the silicon pillar facing tothe stacked layer body, a charge storage layer provided on a surface ofthe tunnel insulator facing to the stacked layer body, a block insulatorprovided on a surface of the charge storage layer facing to the stackedlayer body, the block insulator being in contact with the electrodefilm, and an embedded portion provided in the silicon pillars.

Descriptions will be hereinbelow provided for the embodiment whilereferring to the drawings.

Descriptions will be hereinbelow provided for a nonvolatilesemiconductor memory device according to the embodiment.

FIG. 1 is a cross-sectional view showing a nonvolatile semiconductormemory device according to the embodiment. The descriptions will beprovided by use of a XYZ-coordinate system. The X direction is adirection from the front to the back of the sheet on which the drawingis depicted. The Y direction is a direction from the right to the leftof the sheet on which the drawing is depicted. The Z direction is adirection from the bottom to the top of the sheet on which the drawingis depicted. In the nonvolatile semiconductor memory device according tothe embodiment, an impurity-diffused layer as a back gate is provided inan upper portion of a silicon substrate 1.

As shown in FIG. 1, a back gate insulator 2 and a back gate conductor 3are provided on the silicon substrate 1.

A stacked layer body 6 is provided on the back gate conductor 3. Thestacked layer body 6 is obtained by alternately stacking an insulator 4and an electrode film 5 one on another. A silicon oxide film, forexample, is used for each insulator 4. A poly-crystalline silicon film,for example, is used for each electrode film 5. Each electrode film 5 isused as a control gate electrode of a memory cell, which will bedescribed later. Each insulator 4 has a function of insulatingneighboring electrode films 5 across the insulator 4. FIG. 1 shows thestacked layer body 6 in which four insulators 4 and four electrode films5 are stacked one on another alternately. However, the layered number isnot limited to the above case. An isolation insulator 7 is provided onthe stacked layer body 6. A silicon oxide film, for example, is used forthe isolation insulator 7.

A plurality of silicon pillars 81 extending virtually perpendicularly tothe silicon substrate 1 are provided to be surrounded by the stackedlayer body 6 and the isolation insulator 7. In this respect, the siliconpillars 81 and a silicon connection portion 82, which will be describedlater, jointly constitute a silicon film 8. A poly-crystalline siliconfilm containing fluorine is used for the silicon film 8. The siliconfilm 8 functions as a channel in the nonvolatile semiconductor memorydevice according to the embodiment.

Descriptions will be hereinbelow provided for a concentration of thefluorine contained in the poly-crystalline silicon. FIG. 2 is a diagramshowing a resistivity of poly-crystalline silicon, in which aconcentration of phosphorus is 4×10¹⁸ cm⁻³, against an atomicconcentration of fluorine contained in the poly-crystalline silicon. Asshown in FIG. 2, when the concentration of fluorine in thepoly-crystalline silicon is equal to or greater than 2×10¹⁹ cm⁻³, theresistivity of the poly-crystalline silicon decreases because danglingbonds in grain boundaries of the poly-crystalline silicon are terminatedby fluorine atoms. On the other hand, when the concentration of thefluorine in the poly-crystalline silicon is equal to or greater than2×10²¹ cm⁻³, the resistivity increases because fluorine is present inthe crystal grains of the poly-crystalline silicon. In this respect,when the concentration of fluorine in the silicon film 8 is converted tothe atomic composition expressed in percentage, 2×10¹⁹ cm⁻³ isequivalent to 0.04%, and 2×10²¹ cm⁻³ is equivalent to 4%. In a casewhere the concentration of fluorine in the silicon film 8 is in a rangeof 2×10¹⁹ cm⁻³ to 2×10²¹ cm⁻³, namely 0.04% to 4%, the electron mobilityincreases in a channel, and the resistivity accordingly decreases.Incidentally, the concentration of fluorine in the embodiment isobtained by SIMS (Secondary Ion Mass Spectrometry) using cesium ions.

In the embodiment, the inclusion of fluorine with the above-mentionedconcentration in the silicon film 8 reduces the trap density which isattributable to the dangling bonds in the grain boundaries in thepoly-crystal of the silicon film 8 as the channel, and enhances theelectron mobility in the channel. In a case where the cross-sectionalarea of the silicon pillars 81 becomes larger from a lower portiontoward an upper portion, the number of fluorine atoms contained in thesilicon pillars 81 may be larger in the uppermost portion of the siliconpillars 81 than in the lowermost portion of the silicon pillars 81.Particularly, the number of fluorine atoms may become larger toward theupper portion of the silicon pillars 81.

The silicon pillars 81 are arrayed in a matrix at equal intervals on theXY plane. The shape of each silicon pillar 81 is a hollow conic shape,an elliptic conic shape, a hollow cylindrical shape or an ellipticcylindrical shape, for example. The cross-sectional shape of eachsilicon pillar 81 viewed in the Z direction is a circular shape or anelliptic shape, for example. In a case where the cross-sectional shapeof the silicon pillar 81 is a circular shape, the diameter of the holeis 70 nm, for example, while the height of the silicon pillar 81 is 2.1μm, for example.

The silicon connection portion 82 to connect lower end portions of therespective paired silicon pillars 81 together is provided in the backgate conductor 3. The silicon connection portion 82 is made frompoly-crystalline silicon containing fluorine, for example.

A tunnel insulator 9 is provided on a surface of each silicon pillar 81which faces to the stacked layer body 6. A silicon oxide film, forexample, is used for the tunnel insulator 9.

A charge storage layer 10 is provided on a surface of the tunnelinsulator 9 which faces to the stacked layer body 6. A silicon nitridefilm, for example, is used for the charge storage layer 10.

A block insulator 11 is provided on a surface of the charge storagelayer 10 which faces to the stacked layer body 6, and is in contact withthe electrode films and the insulators 4. A silicon oxide film, forexample, is used for the block insulator 11.

It should be noted that the films of the tunnel insulator 9, the chargestorage layer 10 and the block insulator 11 are provided to surround notonly the silicon pillars 81 but also the silicon connection portion 82.

An embedded portion 12 extending in the layered direction of the stackedlayer body 6 is provided in each silicon pillar 81 of the silicon film8. It is desirable that the embedded portion 12 should be an insulatingportion containing fluorine, for example. However, the embedded portion12 does not necessarily have to contain fluorine. In the case where theembedded portion 12 is an insulating portion, the interface statedensity in the interface between the corresponding silicon pillar 81 andthe embedded portion 12 can be reduced. For this reason, when no voltageis applied to the gate electrode, it is possible to inhibit the flow ofan electric current into the channel. A silicon oxide film containingfluorine, for example, is used for the embedded portion 12. Instead, theembedded portion 12 may be made of a film containing fluorine such as asilicon nitride film, a silicon oxynitride film, or a layered film of asilicon oxide film and a silicon nitride film.

Fluorine atoms are diffused from the embedded portions 12 into thepoly-crystalline silicon in the silicon pillars 81 in contact with theembedded portions 12 and the silicon connection portion 82, andterminate dangling bonds in the poly-crystalline silicon.

In a case where dangling bonds in the poly-crystal are present in theinterface between the silicon film 8 and each embedded portion 12, theelectron mobility in the channel decreases. However, in the embodiment,the dangling bonds in the interface between the silicon film 8 and theembedded portion 12 are sufficiently terminated by using fluorine,because the embedded portion 12 contains fluorine during the filmformation. This termination inhibits the decrease in the electronmobility in the channel.

Each embedded portion 12 needs to contain fluorine during the filmformation. On the other hand, the embedded portion 12 no longer has tocontain fluorine after fluorine is diffused into the poly-crystallinesilicon. The concentration of fluorine contained in the embedded portion12 during the film formation is equal to or greater than 0.1%, forexample, as the atomic composition expressed in percentage.

In the BiCS structure shown in the embodiment, the area of the contactbetween the embedded portion 12 and the silicon pillar 81 is smallerthan the area of the contact between the tunnel insulator 9 and thesilicon pillar 81. On the other hand, in a planar type nonvolatilesemiconductor memory device formed on an SOI (silicon-on-insulator)substrate, an insulator is formed in the silicon substrate, while atunnel insulator, a charge storage layer, a block insulator and anelectrode film are formed on the silicon layer in the surface of the SOIsubstrate. Since the area of the contact between the tunnel insulatorand the silicon substrate is almost equal to the area of the contactbetween the insulator in the SOI substrate and the silicon substrate,the BiCS structure can reduce the interface state in the interfacebetween the embedded portion 12 and the silicon pillar 8 by using asmaller amount of fluorine than the conventional planar type nonvolatilesemiconductor memory device. Thus, the BiCS structure is advantageous inthat metal interconnections are less likely to corrode due to fluorine.

The shape of each embedded portion 12 is a conic shape, an ellipticconic shape, a cylindrical shape or an elliptic cylindrical shape, forexample. The cross-sectional shape of the embedded portion 12 viewed inthe Z direction is a circular shape or an elliptic shape, for example.The embedded portion 12 may be in a reverse tapered shape in which thecross-sectional area of the cross-sectional circle of the embeddedportion 12 viewed in the Z direction becomes smaller toward thelowermost layer of the stacked layer body 6.

In the case where the embedded portion 12 is in the reverse taperedshape, the embedded portion 12 has a larger cross-sectional area andaccordingly contains a larger number of fluorine atoms toward thetopmost layer of the stacked layer body 6. Thus, as shown in FIG. 3, thepoly-crystalline silicon film becomes more dominant toward the lowermostportion of the silicon pillar 81. In the case where the volume of thesilicon pillar 81 is larger in the upper portion than in the lowerportion, the upper and lower portions of the silicon pillar 81 has asmall difference in the number of fluorine atoms per unit volume. Inother words, the electron mobility is equalized throughout the siliconpillar 81, and the reliability of the nonvolatile semiconductor memorydevice can be enhanced.

Stacked films of memory protection insulators 13, select gate electrodes14 and insulation layers 15, are sequentially provided on the isolationinsulator 7. Silicon films 16 are provided in the staked films to extendin a direction virtually perpendicular to the silicon substrate 1, andare connected to the silicon film 8. Gate insulators 17 are provided tosurround the respective silicon films 16. Incidentally, the siliconfilms 16 are made of a poly-crystalline silicon, and thepoly-crystalline silicon may contain fluorine. The select gateelectrodes 14 have plate-like shapes which extend in parallel to the Xdirection, and are formed to be electrically insulated and isolated fromone another.

The embodiment provides the nonvolatile semiconductor memory devicehaving the three-dimensional structure with the silicon film 8containing fluorine as the channel. Thereby, the embodiment can providethe nonvolatile semiconductor memory device which inhibits the decreasein the electron mobility.

Furthermore, the embodiment makes it possible to enhance the electronmobility in the channel, because the embodiment sufficiently terminatesthe dangling bonds in the interface between the silicon film 8 and theembedded portions 12 by use of fluorine.

Descriptions will be hereinbelow provided for a method of fabricating anonvolatile semiconductor memory device according to the embodiment.

FIGS. 4A to 6D are cross-sectional views showing the method offabricating a nonvolatile semiconductor memory device according to theembodiment, which are taken along the YZ plane.

As the back gate, the impurity-diffused layer is formed in an upperportion of the silicon substrate 1 by ion-implantation. Subsequently, asshown in FIG. 4A, the back gate insulator 2 and the back gate conductor3 are formed on the silicon substrate 1.

Thereafter, as shown in FIG. 4B, an opening portion 18 is formed byetching apart of the back gate conductor 3 using lithography and RIE(reactive ion etching). The opening portion 18 is provided for thepurpose of forming the silicon connection portion 82, to which thebelow-described paired silicon pillars 81 are connected. Incidentallythe shape of the opening portion 18 viewed in the Z direction is astrip-like shape, for example.

Afterward, as a sacrifice film, a SiN film is deposited and therebyembedded in the opening portion 18, as shown in FIG. 4C. The SiN filmabove the back gate conductor 3 is removed by a CMP (Chemical MechanicalPolishing). Thereby, the sacrifice film 19 is formed in the openingportion 18.

As shown in FIG. 4D, the stacked layer body 6 is formed by stacking theinsulator 4 and the electrode film 5 alternately one after another onthe back gate conductor 3 and the sacrifice film 19. Subsequently, theisolation insulator 7 is formed on the stacked layer body 6.

After that, as shown in FIG. 4E, through holes 20 are formed to reachthe two end portions of the sacrifice film 19, by etching the isolationinsulator 7 and the stacked layer body 6 by lithography and RIE untilthe etching reaches the sacrifice film 19. Such through holes 20 areformed at equal intervals in a matrix in the XY plane.

Subsequently, as a sacrifice film, a SiN film is deposited and therebyembedded in each through hole 20, as shown in FIG. 4F. A sacrifice film21 is formed in each through hole 20 by CMP.

As shown in FIG. 5A, the sacrifice film 19 and the sacrifice films 21are removed by wet etching using a hot phosphoric acid solution, forexample. Thereby, the two end portions of the now-defunct openingportion 18 respectively communicate with the paired through holes 20,and an opening portion 22 shaped like the letter U is accordinglyformed. The opening portion 22 is formed from the opening portion 18 andthe through holes 20.

As shown in FIG. 5B, the block insulator 11, the charge storage layer 10and the tunnel insulator 9 are sequentially formed in the entire insideof the opening portion 22.

Amorphous silicon 23 is formed on the tunnel insulator 9 inside theopening portion 22. In this process, the amorphous silicon 23 is notfully embedded in the opening portion 22, and a space portion 12 a isaccordingly left.

Subsequently, as shown in FIG. 5C, the embedded portions 12 eachextending in the layered direction of the stacked layer body 6, to whichfluorine is added, are formed on the inner surface of the amorphoussilicon 23 in the stacked layer body 6. Each embedded portion 12 is asilicon oxide film formed by plasma CVD (Chemical Vapor Deposition) inwhich a concentration of fluorine is 1%, for example. The silicon oxidefilm, to which fluorine is added, is formed by plasma CVD using a mixedgas of SiH₄, SiF₄ and N₂O, for example. Incidentally, it is desirablethat the concentration of fluorine needed to diffuse fluorine into thesilicon film 8 should be not less than 0.1% but not greater than 10% asthe atomic composition expressed in percentage. A silicon oxide film inwhich the concentration of fluorine is not less than 0.1% enhances theelectron mobility in a transistor using poly-crystalline silicon. On theother hand, in a case where the concentration of fluorine is not lessthan 10%, it is difficult to form a silicon oxide film in which theelectron mobility is equalized. In addition to the silicon oxide film, asilicon nitride film, a silicon oxynitride film, a layered film of asilicon oxide film and a silicon nitride film, or the like is used forthe embedded portions 12. Incidentally, the embedded portions may beformed as portions containing fluorine and embedded in through holesformed in the silicon pillars 81.

Subsequently, each embedded portion 12, the amorphous silicon 23, theblock insulator 11, the charge storage layer 10 and the tunnel insulator9 protruding from the separation insulator 7 are removed by CMP, andthereby are flattened.

Thereafter, as the silicon film 8, a poly-crystalline silicon film isformed by crystallizing the amorphous silicon 23 through a heattreatment at a temperature in a range of 600° C. to 1250°, for example,at a temperature of 900° C. for one minute. During this step, thefluorine atoms in the embedded portions 12 are diffused into thepoly-crystalline silicon film to form the silicon film 8 containingfluorine. As shown in FIG. 5D, portions of the silicon film 8, which areformed in the respective through holes 20, are termed as the siliconpillars 81. A portion of the silicon film 8, which is formed in theopening portion 18 so as to be connected to the silicon pillars 81, istermed as the silicon connection portion 82. The segregation of thediffused fluorine atoms in the grain boundaries in the poly-crystalcauses fluorine to terminate the dangling bonds in the grain boundaries.Accordingly, the electron trap density can be reduced in the grainboundaries, and the electron mobility can be enhanced in the channelmade of the poly-crystal, which is the silicon film 8.

Each embedded portion 12 extends in the Z direction, and the sidesurface of the embedded portion 12 is covered with the silicon film 8.In other words, the entire side surface of the embedded portion 12 is incontact with the silicon film 8. The structure mentioned above inhibitsfluorine from diffusing into portions other than the silicon film 8, andthe fluorine efficiently diffuses from the embedded portion 12 into thesilicon film 8.

Use of a silicon oxide film for the embedded portions 12 facilitates thediffusion of fluorine atoms into the poly-crystalline silicon filmserving as the silicon film 8. For this reason, the heat treatment maybe performed at a lower temperature. On the other hand, use of a siliconnitride film for the embedded portions 12 makes it more difficult todiffuse fluorine atoms. For this reason, the use of the silicon nitridefilm requires the heat treatment at a higher temperature than the use ofthe silicon oxide film. In this case, it is possible to make theelectron mobility stable irrespective of the heat treatment step afterthe film formation of the embedded portions 12.

Afterward, as the memory protection insulator 13, a silicon nitride filmis formed above the stacked layer body 6, as shown in FIG. 5D. Afterthat, a memory isolation groove 24 extending in the X direction isformed between the silicon pillars 81. Such memory isolation grooves 24are provided at equal intervals in the XY plane. Subsequently, as thememory protection insulator 13, a silicon nitride film is embedded inthe memory isolation groove 24, as shown in FIG. 6A.

Thereafter, as shown in FIG. 6B, the select gate electrode 14 and theinsulator layer 15 are formed. A poly-crystalline silicon film is usedfor the select gate electrode 14, and a silicon oxide film, for example,is used for the insulator layer 15.

Afterward, as shown in FIG. 6C, through holes 25 are formed in portionsof the stacked films above the silicon pillars 81 by lithography andRIE. The through holes 25 are formed to expose the respective siliconpillars 81.

Afterward, as shown in FIG. 6D, the gate insulators 17 are formed on theinner surfaces of the through holes 25, respectively. Furthermore, asthe silicon films 16, the poly-crystalline silicon film, for example, isembedded on the inner surfaces of the respective gate insulators 17.

Multiple mutually-isolated source lines SL extending in the X directionare formed, which are connected to the top portion of the silicon film16 on one of the paired silicon pillars 81.

A plurality of mutually-isolated bit lines BL extending in the Ydirection are formed, which are connected to the top portion of thesilicon film 16 on the other one of the paired silicon pillars 81.

The nonvolatile semiconductor memory device according to the embodimentis formed through the foregoing steps.

As described above, fluorine is included in the silicon pillars 81 inthe nonvolatile semiconductor memory device according to the embodiment.This structure reduces the electron trap density in the poly-crystal ofthe silicon film 8 serving as the channel, and accordingly enhances theelectron mobility in the channel.

In addition, in the case where fluorine is included in the silicon film8 formed from the silicon pillars 81 and the silicon connection portion82, the electron trap density decreases in the poly-crystal of thesilicon film 8 serving as the channel, and the electron mobility can beaccordingly enhanced in the channel.

Furthermore, in the method of fabricating a nonvolatile semiconductormemory device according to the embodiment, the fluorine-containingembedded portions 12 are formed in contact with the correspondingsilicon pillars 81, and fluorine atoms in the embedded portions 12diffuse into the silicon pillars 81 or the silicon connection portion 82through the heat treatment. Accordingly, it is possible to make fluorineatoms diffuse from the embedded portions 12 into the silicon pillars 81or the silicon connection portion 82 not only in the front end but alsocontinuously in the back end.

It should be noted that, as shown in FIG. 7 the fluorine-containingembedded portion 12 may be provided in the silicon connection portion 82in the foregoing nonvolatile semiconductor memory device according tothe embodiment. In this case, fluorine is supplied to the siliconconnection portion 82 in the silicon film 8. This further decreases theelectron trap density in the silicon film 8, and accordingly enhancesthe electron mobility in the channel.

It should be noted that, although the foregoing descriptions have beenprovided for the embodiment on the assumption that the lowermost ends ofthe silicon pillars 81 are connected together via the silicon connectionportion 82, the silicon pillars 81 may be instead provided independentlyof each other without being provided with the silicon connection portion82.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A method of fabricating a semiconductor device,comprising: stacking an insulator and an electrode film above asubstrate alternately to provide a stacked layer body; forming throughholes extended to a stacking direction of the stacked layer body;stacking a block insulator, a charge storage layer, a tunnel insulatorand a silicon film sequentially on an inner surface of the throughholes; embedding an embedded portion contained with fluorine andextended to the stacking direction of the stacked layer body on an innersurface of the silicon film; and diffusing fluorine into the siliconfilm by heating.
 2. The method of claim 1, wherein a fluorineconcentration contained in the silicon film is ranged from 0.1% to 10%as atomic percentage in embedding the embedded portion.
 3. The method ofclaim 1, wherein the embedded portion is provided to have a reversetapered shape in embedding the embedded portion.
 4. A method offabricating a semiconductor device, comprising: providing a firstinsulator on a substrate; etching the first insulator to provide agroove; embedding a sacrifice film into the groove; stacking aninsulator and an electrode film on the first insulator and the sacrificefilm alternately to provide a stacked layer body; forming through holesextended to a stacking direction of the stacked layer body; removing thesacrifice film to provide an opening portion which communicates with onepair of lower portions of the through holes; stacking a block insulator,a charge storage layer, a tunnel insulator and a silicon filmsequentially on exposed surfaces of the through holes and the openingportion; embedding an embedded portion contained with fluorine, theembedded portion being in contact with the silicon film; and diffusingfluorine into the silicon film by heating.
 5. The method of claim 4,wherein a fluorine concentration contained in the silicon film is rangedfrom 0.1% to 10% as atomic percentage in embedding the embedded portion.6. The method of claim 4, wherein the embedded portion is provided tohave a reverse tapered shape in embedding the embedded portion.